Static Random Access Memories (SRAM) are widely used in computer systems and other applications to store data. U.S. Pat. No. 4,125,854 (the '854 patent) to Vern McKinney and T. C. Chan and U.S. Pat. No. 5,298,782 to Sundaresan disclose a layout for an SRAM memory cell, both of which are incorporated herein by reference.
Two of the features that are relevant in the design of the memory cell are the total area occupied by the memory cell and the aspect ratio. It is desirable to make the silicon area occupied by the memory cell as small as practical so as to increase the density of the memory array. A memory cell that occupies a small area of silicon permits more memory cells to be fabricated on a single silicon chip of a given size.
The aspect ratio is a measure of the squareness of the memory cell. The height of the memory cell is divided by the width to produce a numerical value of the aspect ratio. The height is measured along the bit line, the width along the word line. For example, if the height of the memory cell is 11 microns and the width is 6 microns, this produces a memory cell having an aspect ratio of approximately 1.83 and an area of 66 square microns. On the other hand, a memory cell which is 9 microns in height and 7.5 microns in width has an aspect ratio of 1.2 and occupies just slightly more area, 67.5 microns. A perfectly square memory cell would have an aspect ratio of 1.0.
A square area for the entire memory array and for the entire chip, including the peripheral circuits, is often preferred. Use of a memory which has a low aspect ratio, in the range of 1.1 or 1.2 is advantageous in those designs where a square die is desirable for the entire memory array. It is therefore helpful to provide a memory cell which has not only a low area but also a low aspect ratio.
FIG. 1 shows the layout of a memory cell according to the prior art. As can be seen by viewing this layout, it is generally rectangular in shape, rather than generally square. It has an aspect ratio of approximately 1.63 as can be determined by dividing its height by its width. Accordingly, if this memory cell is repeated throughout the chip, the array of memory cells will be more rectangular than square. The design of FIG. 1 therefore makes it more difficult to obtain a square final chip which occupies a minimal silicon area.
The memory cell includes the first polysilicon layer 2 and a second polysilicon layer 3. A third polysilicon layer is also present, however, its layout and position is similar to that shown in FIG. 6 of the present invention and therefore is not repeated here. The first layer 2 of polysilicon includes the gate electrodes of the wordline 5 and the gate electrodes 7 of the storage transistors. The wordline 5 has a significant bend as shown at position 6 between the two bit lines of the memory cell. The bitline is therefore, not straight through the memory cell and instead undergoes a significant change of direction. If a straight line 8 is drawn through any portion along the length of wordline 5, the change of direction of the wordline is sufficiently great that it completely deviates from the straight line 8, which is a greater distance than its own width.
In addition, the gates of the storage transistors 7, are perpendicular to the direction of the gate electrodes of the word line 5. The gate electrodes 7 are not straight and also undergo a bend. Further, the channel regions underlying the gate electrodes 7 of the storage transistors do not run in the same direction and are not parallel to the channel regions underneath the word line gate electrode 5, as can be seen viewing FIG. 1.